The present invention relates, in general, to testing of memory arrays and, more specifically, to a method of efficiently repeating test instructions and to a test controller for use therewith.
Memory BIST controllers use a very wide instruction word (e.g., 40 bits) for programming algorithms. A memory test developer may specify as many instructions as required in a memory BIST microprogram memory array to perform a memory test. However, since the developer wishes to keep the number of gates required to implement a word in the memory array to a minimum, it is desirable to keep the number of instructions to a minimum. Generally, each word requires about 250 gates.
Many memory test algorithms, particularly March algorithms, repeatedly perform the same operations but with opposite data or parameters or traverse an address space in one direction and then in the opposite direction. The conventional way of doing this utilizes many more instructions than are required. This requires many more gates than required.
Kalter et al U.S. Pat. No. 5,961,653 granted on Oct. 5, 1999 for xe2x80x9cProcessor based BIST for an embedded memoryxe2x80x9d describes a processor based BIST macro for testing memory embedded in logic and includes a base ROM which is structured to have test instructions written into it in microcode form. The base ROM component is configured having 160 addresses by 34 bits wide, providing for a total of 160 test instructions, branch statements to be used in conjunction with the instructions and a scannable ROM. The scannable ROM is configured having 34 addresses by 34 bits wide. The arrangement allows for altering, adding, deleting, changing the sequence of any test patterns and looping within a single pattern or any group of patterns. The 34 address lines in the scannable ROM allow for 17 branch instructions which bound the beginning and end of each test pattern produced from the base ROM and 17 extra instruction words to accommodate any modifications or changes. The scannable ROM addresses are typically sequenced from 192 through 225. The two ROMs and are multiplexed together onto a 34 bit test buss controlled by the sequencer.
Illes et al U.S. Pat. No. 5,925,145 granted on Jul. 20, 1999, for xe2x80x9cIntegrated circuit Tester with Cached Vector Memoriesxe2x80x9d discloses an integrated circuit tester which includes a set of nodes providing test access to separate terminals of an IC and each carrying out a sequence of actions at the terminal in response to test vector sequences. Each node includes a low speed vector memory supplying test vectors during the test. A host writes vectors into the vector memories before the test sending them over a common bus to vector write caches within each node which compensate for access speed limitations of the vector memory. During the test, blocks of vectors are read out of the vector memory at a low rate and written into a high speed read cache array. An instruction processor within each node reads individual vectors read out of the read cache array at a high rate and uses them for controlling test operations at the node during each cycle of the test. The read cache array also allows the instruction processor to re-use repeated vector patterns, thereby reducing the number of vectors that must be distributed to the nodes.
Ozawa et al. U.S. Pat. No. 6,038,649 granted on Mar. 14, 2000 for xe2x80x9cAddress Generating Circuit for Block Repeat Addressing for a Pipelined Processorxe2x80x9d discloses an address generating circuit for repeating a selected block of instructions. An instruction address maintained by a program counter is compared to register that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions. A Block repeat count register maintains a repeat count. A zero detection circuit delays decrements by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to the program counter. The zero detection circuit outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt. The zero detection circuit also deactivates the loop-end control signal for the number of clock cycles equivalent to the depth of the pre-fetch pipeline during the final repeat loop iteration(s) so that a loop with a block size less than or equal to the depth of the prefetch pipeline can be repeated the correct number of times.
Heidel et al U.S. Pat. No. 6,108,798, granted on Aug. 22, 2000 for xe2x80x9cSelf programmed built in self test, discloses a Dynamic Random Access Memory (DRAM) with self-programmable Built In Self Test (BIST). The DRAM includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions.
The present invention provides a method for repeating an instruction or a series of consecutively executed instructions with modifications to the instruction fields of each commands as well as a circuit especially adapted to carry out the method.
One aspect of the invention is generally defined as a method for testing memory embedded in an integrated circuit, the method comprising executing each instruction of a plurality of test instructions in sequence, each instruction having an inactive repeat control field except for a last instruction of each of one or more groups of one or more instructions to be repeated, each of the last instruction having an active repeat control field; and, for each instruction having an active repeat control field, executing, in sequence, the instructions of the group of instructions with which each instruction is associated for a predetermined number of repeat cycles for the group; and, for each repeat cycle, modifying predetermined fields of each instruction in accordance with a predetermined field modification instructions for each repeat cycle.
Another aspect of the invention is generally defined as an memory improvement to a test controller for testing a memory array, the controller having a test instruction register array having registers for storing a plurality of test instructions, each register having instruction fields for storing memory addressing sequencing data, write data sequencing data, expect data sequencing data and operation data specifying an operation to be performed on the memory array, the improvement comprising a repeat module for repeating a group of one or more test instructions with modified data, the repeat module including storage means for storing instruction field modification data; and each register of the test instruction register array including an instruction field for enabling or disabling the repeat module.
A still further aspect of the present invention is generally defined as a test controller for use in testing memory imbedded in an integrated circuit, the test controller comprising a scannable microcode register array having one or more instruction registers for storing a plurality of test instructions for performing a test of the memory in accordance with a predetermined test algorithm; a pointer controller for selecting one of the test instructions for execution and determining a next instruction for execution in accordance with conditions stored in each the test instruction; an instruction repeat module for reading address sequencing, write data sequencing, expect data sequencing data from a current test instruction and outputting address sequencing, write data sequencing, expect data sequencing data, the repeat module being responsive to instruction repeat data in the current test instruction for repeating an operation specified in the test instruction with different data; a sequencer responsive to an operation code in the current instruction for performing a predetermined operation on the memory under test; and an address generator and a data generator responsive to the output address sequencing, write data sequencing, expect data sequencing data for application to a memory under test in accordance with an operation specified in the current instruction.